Larger computer and control systems are often distributed on a plurality of circuit boards, each having its own clock source. Typically, real time applications require accurate phase aligned reference clock signals in order to guarantee that the operation will be unaffected in case of a failure of a clock source or failure of a unit incorporating such a clock source. It is known to generate a common system clock from at least one of a plurality of clock sources, such that a system reference clock signal is provided, preferably with insignificant phase delays, to each of the plurality of boards. Should any circuit board or any clock source malfunction, the function of the system clock should be restored or retained. It should also be possible to replace a single circuit board without seriously interrupting the operation of the remaining system, i.e. hot swapping circuit boards.
Prior art document U.S. Pat. No. 6,194,969 shows a redundant clock system comprising a first clock board and a second clock board, a system board and a system controller. Each clock board comprises at least one clock source. In operation, one clock board is providing a master clock signal while the other is providing a slave aligned clock signal. If the master clock signal is found to loose as little as one clock edge, an input clock failure is identified by the system board and a switchover is made, for instance within three clock cycles, to the redundant slave clock signal in phase alignment with the master clock signal. Any of the first or second clock boards may be hot swapped with a third clock board.
In prior art document U.S. Pat. No. 6,194,969 two phase-locked signals are provided for redundancy. To make use of these redundant clock signals, every receiver needs two inputs and selection circuitry to switch between the redundant clock signals.
Prior art document U.S. Pat. No. 4,282,493 shows a redundant clock generating circuitry for providing an uninterrupted clock signal. Two clock modules are provided each comprising a first PLL oscillator and a second PLL oscillator monitoring the first PLL oscillator and providing an out-of-lock signal upon detection of any disparity there-between. One clock is master and the other is slave. Switching the master from one clock module to the other will not cause any phase discontinuities or momentary bit transitions on output clock signals because the master and slave clock are phase locked with regard to one another prior to and after switching. Switching from one clock to the other may be initiated upon detection of a malfunction as indicated by an out-of-lock signal.
If there is a failure on the master clock module in U.S. Pat. No. 4,282,493, the signal from the slave unit will seamlessly take over. However, when the slave module takes over as master, the signal from this board is physically driven through the board of the previous master. If the previous master board is removed, all boards of the system will loose their clock signal; i.e. hot-swapping of the clock modules is not possible.
Moreover, apart from the PLL devices used for phase locking of the two sources, U.S. Pat. No. 4,282,493 assumes a PLL in the receiver end and requires additional logic on all boards of the system sharing a common clock in the same manner as in U.S. Pat. No. 6,194,969.